1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly, to a semiconductor device having a circuit associated with a reliability evaluation testing.
2. Description of the Background Art
Recently, together with the advancement of the integration of semiconductor devices and the miniaturization of MOS transistors, a thickness of a gate oxide film of an MOS transistor have been decreasing, leading to the decreased breakdown voltage of the gate oxide film. Therefore a high gate voltage may have an adverse effect on the reliability of an MOS transistor.
In some systems using a semiconductor memory device, a voltage required for an operation of the semiconductor memory device is lower than a power supply voltage of the system itself. In such a case, the power supply voltage for the semiconductor memory device is generally supplied from the power supply voltage of the system itself, by generating an internal power supply voltage required for the operation of the semiconductor memory device by pulling down the voltage inside the semiconductor memory device.
A circuit generating the internal power supply voltage in this manner is called a voltage down converter. Use of such a voltage down converter allows the substantial reduction of the power consumption by the semiconductor memory device thus stabilizing the internal power supply voltage used therein.
Now, the reliability evaluation test will be described.
Generally, a life of a device can be divided into three periods based on the characteristics of failures. That is, an early failure period, followed by a random failure period and a wear-out failure period.
Immediately after the device is put under use, the early failure period starts. During this period, early failures originating from defects at the time of manufacture of the device are revealed. The rate of an early failure rapidly decreases with time.
Then a long random failure period with a low failure rate lasts for a certain period.
As the device approaches the end of its useful life, it enters the wear-out failure period where the failure rate dramatically increases.
The device is desirably used in the random failure period, which is regarded as equivalent to the service life of the device. Therefore, the random failure period is required to last long with a low and constant failure rate, in order to enhance the device reliability.
On the other hand, a screening is indispensable for precluding early failures, in which devices are subjected to accelerated aging for a prescribed time period, whereby defective devices are screened out. A screen testing which ensures that the early failure rate rapidly decreases against time to enable immediate commencement of the random failure period is desirable in order to perform the screening effectively in a short time period.
Currently a high temperature operation test (burn-in test) is generally performed as a screening procedure. The burn-in test allows a direct evaluation of a dielectric film using an actual device. During the burn-in test, every defective factor including a migration of an aluminum interconnection is revealed by applying a high temperature and high-field stresses.
When the device is operated under a high temperature to enhance acceleration, the burn-in test becomes particularly effective.
FIG. 15 is a block diagram showing a configuration of a voltage down converter portion of a conventional semiconductor device adaptable for the burn-in test.
Referring to FIG. 15, the voltage down converter of the conventional semiconductor device includes: a capacitor 212 arranged between an external power supply potential Ext.Vcc and a ground potential; a capacitor 220 arranged between an internal power supply potential Int.Vcc and the ground potential; a reference voltage generation circuit 216 generating a reference potential for internal power supply potential Int.Vcc at a normal operation; a differential amplifier 218 powered by external power supply potential Ext.Vcc and setting an internal power supply potential Int.Vcc of the same level as an output voltage of reference voltage generation circuit 216; and a P channel transistor 214 having a gate receiving a burn-in mode detection signal /STR, a source coupled to external power supply potential Ext.Vcc and a drain coupled to internal power supply potential Int.Vcc.
In a normal mode other than a test mode for the reliability evaluation, burn-in mode detection signal /STR is at a logical high (H) level and P channel transistor 214 is off.
In the test mode for the reliability evaluation, burn-in mode detection signal /STR attains a logical low (L) level and a node supplied with internal power supply potential Int.Vcc and a node supplied with external power supply potential Ext.Vcc are connected together via P channel transistor 214, thus internal power supply potential Int.Vcc is rendered equal to external power supply potential Ext.Vcc.
In such a voltage down converter as the one shown in FIG. 15, however, transistor 214, which short-circuits a node receiving external power supply potential Ext.Vcc and a node receiving internal power supply potential Int.Vcc at the time of testing, must be large enough to secure the current driving capability. Such a large transistor required for the testing of semiconductor devices causes a chip area to increase.
A method for rendering internal power supply potential Int.Vcc the same level as external power supply potential Ext.Vcc using an output driving transistor included in a differential amplifier portion is disclosed in Japanese Patent Laying-Open No. 6-103793.
FIG. 16 is a circuit diagram showing a configuration of a voltage down converter disclosed in the aforementioned Japanese Patent Laying-Open No. 6-103793.
The voltage down converter shown in FIG. 16 includes: a reference voltage generation circuit 2100 for generating a reference voltage Vref; a comparator 2200 for receiving and comparing internal power supply voltage Int.Vcc and reference voltage Vref; a driver P5 controlled by comparator 2200 and pulling down external power supply voltage Ext.Vcc to the level of internal power supply voltage Int.Vcc; a burn-in reference voltage generation circuit 2300; series-connected inverters Il and I2 receiving an output of node G3 of burn-in reference voltage generation circuit 2300 as an input; an inverter I3 receiving an output of inverter I2; an N channel transistor N4 having a gate receiving an output of inverter I3 and connecting an output node G1 of comparator 2200 and a node G2 connected to a gate of driver P5; a P channel transistor P3 having a gate receiving the output of inverter I2 and connecting node G1 and node G2; and an N channel transistor N5 having a gate receiving the output of inverter I2 and coupling node G2 with a ground potential Vss.
Comparator 2200 includes an N channel transistor N3 having a gate receiving reference voltage Vref and a source coupled to ground potential Vss, an N channel transistor N1 having a gate receiving reference voltage Vref and connecting a drain of N channel transistor N3 and node G1, an N channel transistor N2 having a gate receiving internal power supply potential Int.Vcc and a source connected to the drain of N channel transistor N3, a P channel transistor P2 having a gate receiving a drain potential of N channel transistor N2 and coupling the drain of N channel transistor N2 and external power supply potential Ext.Vcc and a P channel transistor P1 having a gate receiving a potential from the drain of N channel transistor N2 and coupling node G1 and external power supply potential Ext.Vcc.
FIG. 17 is a waveform diagram illustrating an operation of the voltage down converter shown in FIG. 16.
Referring to FIGS. 16 and 17, the voltage down converter operates normally during the time period t1-t2.
Internal power supply potential Int.Vcc is applied to each circuit block such as a memory element in a chip, as well as to the gate of N channel transistor N2 in comparator 2200.
Therefore, when internal power supply potential Int.Vcc attains lower than the potential of reference voltage Vref because of the current consumption by each circuit block such as a memory element inside a chip while the internal power supply potential Int. Vcc is supplied to the device, the potential at output node G1 of comparator 2200 is lowered.
Then driver P5 is rendered conductive, reducing the voltage drop in internal power supply potential Int.Vcc.
On the other hand, when internal power supply potential Int.Vcc attains higher than the potential of reference voltage Vref and the level of the potential at output node G1 of comparator 2200 goes higher, the voltage drop at driver P5 is increased accordingly, thereby reducing internal power supply potential Int.Vcc down to the potential of reference voltage Vref.
During the time period t1-t2, the potential at output node G3 of burn-in reference voltage generation circuit 2300 is at an L level. Accordingly, N channel transistor N4 and P channel transistor P3 are both conductive, nodes G1 and G2 are connected and N channel transistor N5 is turned OFF.
From time t2 to t3, output node G3 of burn-in reference voltage generation circuit 2300 attains an H level. In response, both N channel transistor N4 and P channel transistor P3 are turned OFF. N channel transistor N5 turns ON and the potential at node G2 attains an L level.
Thus driver P5 is rendered conductive, allowing external power supply potential Ext.Vcc to be applied to the chip via driver P5 with little voltage drop. At this point, output node G1 of comparator 2200 at an H level does not affect node G2 because P channel transistor P3 and N channel transistor N4 are both at an OFF-state.
In a conventional semiconductor device using a voltage down converter such as those shown in FIGS. 15 and 16, internal power supply potential Int.Vcc of one level generated by one voltage down converter is used.
In this case, in a semiconductor memory device, following problems arise, for example.
In general a memory cell array consumes a large current compared with a peripheral circuitry. To achieve reduction in power consumption, therefore, internal power supply potential Int.Vcc supplied to the memory cell array is decreased. When such a decreased internal power supply potential Int.Vcc generated by one voltage down converter is applied to the peripheral circuitry portion, however, the peripheral circuitry cannot achieve a required high-speed operation.
Meanwhile, internal power supply potential Int.Vcc can be increased in order to obtain a high-speed operation of the peripheral circuitry. In a conventional semiconductor memory device, however, an increased internal power supply potential Int.Vcc is also applied to the memory cell array because there is only one voltage down converter. The reduction of power consumption cannot be achieved if such a large internal power supply potential Int.Vcc is supplied to the memory cell array.
In a voltage down converter as shown in FIG. 16 where a transfer gate is inserted between the comparator output and the gate of the driver, the transfer gate must be large enough to ensure a sufficiently high speed response at the normal operation. This leads to increased chip area.
An object of the present invention is to provide a semiconductor device which allows an effective reliability evaluation testing and realizes the high speed operation and the reduction in power consumption.
The present invention is, to be brief, a semiconductor device including a first power supply terminal, a second power supply terminal, a control circuit and a first voltage down converter.
The first power supply terminal receives a first power supply potential. The second power supply terminal receives a second power supply potential higher than the first power supply potential. The control circuit generates a test mode signal in response to an externally applied designation. The first voltage down converter receiving the first power supply potential and the second power supply potential pulls down the second power supply potential to generate a first intermediate potential. The first voltage down converter includes a first output node, a first reference potential generation circuit generating a first reference potential which is a reference for the first intermediate potential, a first internal node receiving the second power supply potential, and a first comparison circuit receiving and comparing the first reference potential and a potential at the first output node, the first comparison circuit having a first inactivation circuit inactivating a comparison operation in response to the test mode signal, and a first drive circuit supplying a current from the first internal node to the output node in accordance with the output of the first comparison circuit at the time of inactivation of the test mode signal and connecting the first output node and the first internal node at the time of activation of the test mode signal.
An advantage of the present invention is, therefore, that an additional element for conducting an external power supply potential line and an internal power supply potential line at the time of burn-in testing is not required because an output driving P channel transistor of a voltage down converter generating an internal power supply potential can be rendered conductive, hence the required area is reduced. A further advantage of the present invention is that the response of the voltage down converter will not be adversely affected at the time of normal operation, because the comparator itself is inactivated at the time of burn-in testing and an output of the comparator is supplied directly to a gate of the driving P channel transistor and not via a transfer gate.